The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the course of integrated circuit evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs.
As semiconductor device sizes continue to shrink, it has become increasingly more difficult to make accurate measurements of various parts of a semiconductor device. For example, it may be desirable to measure mechanical and/or electrical characteristics of a low-k dielectric material of an IC to ascertain when and where potential cracking might occur within the IC. However, due to the shrinking sizes of the ICs and the components therein, existing mechanical and electrical measurements of the low-k dielectric materials are performed after the IC has been packaged. This requires longer verification time and additional resources, which may increase fabrication costs.
Therefore, while existing methods of measuring low-k dielectric materials in an IC have been generally adequate for their intended purposes, they have not been entirely satisfactory in every aspect.